Integrated circuits (ICs) and other semiconductor devices are sensitive to Electrostatic Discharge (ESD) events. Generally speaking, an ESD event results from the quick discharge of a previously charged object or person, which yields a high current pulse of short duration. For example, a person carrying even a relatively small electric charge, upon inadvertently touching the electrical terminals of an IC, may cause the outright failure of the IC's internal components. Also, in some cases, the degradation caused by ESD may affect the long-term reliability of ICs.
To protect against ESD events, an IC may be provided with circuitry that promotes the safe dissipation of electrostatic discharges. An example of an ESD protection circuit is the N-type Metal-Oxide-Semiconductor (NMOS) or P-type MOS (PMOS) clamp. In the presence of an ESD event, the clamp is configured to become conductive and to cause the excess current to flow to the ground.
The inventors hereof have noted, however, that traditional ESD protection circuitry tends to fail under certain circumstances. For instance, Burn-In (BI) processes that are now commonly used during semiconductor manufacturing can cause Electrical Overstress (EOS) damage in ESD clamps. Other EOS conditions (e.g., noisy power environments, etc.) may also negatively affect the performance of ESD protection circuits.